Making Tokens, Pt. 3: Photolithography

Part three of the Making Tokens series. Part 1 refined sand into 9N polysilicon. Part 2 pulled that into a single-crystal wafer. Now we take that bare wafer and walk it through the most complex manufacturing process on the planet.

What "fabrication" actually is

When people say "fab," they mean the multi-hundred-step process of taking a bare silicon wafer and building hundreds of billions of transistors and metal interconnects on its surface, layer by layer, by repeatedly:

1. Depositing a thin film (silicon dioxide, silicon nitride, copper, cobalt, hafnium oxide, etc.)
2. Coating the film with a photoresist
3. Exposing the photoresist through a patterned mask
4. Developing to remove the exposed (or unexposed) photoresist
5. Etching the underlying film where the resist is gone
6. Stripping the remaining photoresist
7. Cleaning everything
8. Repeat

That list is a simplified patterning sequence, not a complete process recipe. Implantation, annealing, planarization, and interconnect fabrication add many other steps. Layer counts and cycle time vary by chip design and process node.

A wafer repeatedly returns to different tools as the circuit takes shape. Manufacturing time includes both processing and the queues between tools.

An aside, because I have to

I spent a couple of years in undergrad at Northwestern running a chemical vapor deposition rig in a chemistry lab. The job was growing graphene (a single-atom-thick sheet of carbon) on various substrates: silicon wafers with a thin oxide, copper foil, nickel foil. The chemistry is, on paper, embarrassingly simple. You pipe argon into a quartz tube as the carrier gas, hydrogen to clean and reduce the substrate surface, and methane as the carbon feedstock. You ramp the substrate to around 1000 °C. The methane cracks on the hot surface, leaves carbon atoms behind, and (if you have done everything right) those atoms organize themselves into a continuous sheet of graphene one atom thick. You cool it, characterize it under Raman and SEM, and write down what happened.

It almost never worked the same way twice.

The same recipe on the same substrate at the same temperature with the same flow rates would give you beautiful continuous graphene one Tuesday, scattered patches of garbage on Wednesday, and bilayer junk on Thursday. We spent months chasing variables: how thick the native oxide on the silicon was, exactly how clean we got the copper, how fast we ramped temperatures, whether the leak rate on the quartz tube had drifted since the last service, whether someone had opened the door to the fume hood at the wrong moment and let in a little extra humidity. The yield was somewhere around one in five runs producing something we could write about.

Now imagine the fab version of this problem. Deposition thickness, particles, doping, alignment, and etch behavior must stay controlled across a wafer and through many repeated operations. The acceptable limits depend on the layer and the process. Exact yield figures for a particular accelerator are not something I can infer from the transistor count.

The respect I have for what TSMC and ASML and Applied Materials actually accomplish has its roots in the fact that I once tried, badly, to do a single layer of it for a couple of years.

The lithography step is the bottleneck

Of all those steps, the one that gets the headlines is photolithography: transferring patterns to a resist on the wafer. Optical resolution matters, but process-node names are not literal gate lengths. Multi-patterning and the rest of the process also determine the final geometry.

For a long time, the industry used deep ultraviolet (DUV) light at 193 nm, generated by an argon-fluoride excimer laser. With clever tricks (immersion lithography, multi-patterning, off-axis illumination), 193 nm lithography pushed all the way down to the 7 nm node. But by the time you're trying to print features smaller than the wavelength of the light by an order of magnitude, you're doing the optical equivalent of carving a watch movement with a chainsaw.

Advanced processes use both DUV and extreme ultraviolet (EUV) lithography. EUV operates at 13.5 nm and uses reflective optics in a vacuum. It does not mean every layer is printed with EUV, or that all manufacturers switched at exactly the same node.

ASML supplies EUV scanners. Its NXE:3800E uses 0.33 numerical aperture; the EXE:5000 introduces 0.55 NA. These are distinct system families. Machine prices and the number of scanners a fab needs depend on configuration, capacity, and time; they are not fixed constants.

The resources around the wafer

Water. Cleaning requires highly purified water. Plant withdrawal, water consumed, water recycled, and water circulated through a process are different measures. A fab-wide total should name the site, year, and boundary before it becomes a "per wafer" estimate.

Power. Process tools, cooling, and cleanroom air handling all draw power. Neither a single scanner's rating nor a generic fab load describes a specific facility's energy use.

Cleanliness. Particle size and sampling volume belong in any cleanroom claim. The old US "Class 1" convention counted particles per cubic foot, not per cubic meter. Modern ISO classes use a different definition. A tool's local environment may also be cleaner than the surrounding room.

Chemicals. Photoresists, developers, etchants, cleaning agents, and deposition gases all need tight impurity control. This supply chain is part of the manufacturing problem, not a rounding error next to the scanner.

Capital. A single fab, a multi-fab campus, and a multi-year regional investment are different budget boundaries. TSMC's annual reports provide dated investment and operating context. I would not treat an old Arizona campus announcement as the price of one current fab.

Yield and per-die economics

Not every die on a wafer works. Defects, design constraints, and process maturity determine how many are saleable. Larger dies generally expose more area to possible defects, but a generic yield percentage is not a disclosed H100 yield.

The useful cost equation is simple:

Processed-wafer cost ÷ saleable dies = fabrication cost per saleable die.

For an explicitly hypothetical example, a $20,000 processed wafer yielding 50 saleable dies gives $400 of fabrication cost per die. That is not the cost of an H100. Packaging, HBM memory, boards, system integration, development, and vendor margin remain. The sale price of a complete accelerator cannot be compared directly with the purchase price of one bare wafer as a "value-add" multiple.

The geography of all of this

TSMC, Samsung, and Intel are major manufacturers investing in advanced logic processes. Which sites can make which chips changes with process qualification and capacity. A site's country or a company's total fab count does not tell you whether it can manufacture a particular accelerator.

That concentration has geopolitical consequences. It also creates practical deployment constraints: wafer capacity is only one part of the chain. Packaging and memory can be bottlenecks too.

What's next

At the end of this stage, we have dies that still need testing and packaging. An H100-class accelerator combines its logic die with HBM memory and interconnects; the module and server depend on the product variant. It is not thousands of streaming multiprocessors on a universal OAM board.

In Part 4, we use a 100,000-GPU H100 example to calculate power demand. The inputs will be visible, because a plausible-looking number is not the same thing as a checked one.